A memory control device disclosed in Patent Citation 1 is known for instance. This memory control device is composed of a processing module, a bridge module, and a memory module. The processing module is provided with a verification command generating control module, and the bridge module is provided with a verification command response module. The verification command generating control module issues a write command for the memory module to normally terminate the transfer, and then issues a verification command for verifying a transfer state of the write command. The verification command response module responds using a reply packet that has been received corresponding to the transfer of the write command as a read date when the bridge module receives the verification command.
[Patent Citation 1]
    Japanese Patent Application Laid-Open Publication No. 2001-243206